Infineon Technologies AG introduced a family of optical networking integrated circuits (ICs) that are the industry's first to comply with Draft 2.1 of the proposed IEEE 802.17 RPR standard. The new Frea PoS Framer/RPR MAC ICs are the latest addition to Infineon's extensive portfolio of optical network solutions. The single-chip Frea devices integrate functions previously requiring a minimum of four separate components. This is the highest degree of integration of any RPR chip, and can result in significant savings for manufacturers of switches and routers in terms of power consumption, board design complexity and space, software development, and overall system cost. For example, the bill of materials for a typical RPR node implementation, excluding memory, may be as high as $1,650, which is almost $300 greater than the high-end Frea chip. Even greater cost-of-ownership savings can be seen when the benefits of a smaller footprint, lower power, and use of a single software suite are considered. RPR technology i s used to support the use of high-speed Ethernet communications in optical network systems. The Frea chips perform the PoS (Packet-over-SONET) framer, RPR MAC (Media Access Control) and XAUI SerDes (serializer/deserializer) functions that are necessary to deploy RPR in metropolitan area networks (MANs) and wide area networks (WANs). These high integration ICs eliminate the need for external memory by including 1Megabyte of memory on-chip for RPR operation and also a 16-bit 800 MHz SPI-4.2 system interface and a 4-bit 3.125 GHz mate (XAUI) interface, eliminating the need for an external SerDes to link the two chips required for a full RPR implementation.
The RPR technology that is currently being standardized in the IEEE 802.17 committee is gaining wide acceptance in systems that extend Gigabit Ethernet (GbE) into the MAN and WAN environment. It is a Layer Two MAC technology that combines the simplicity and bandwidth efficiency of Ethernet-based networks with the carrier-class features of SONET networks. For carriers, the RPR architecture can provide greater than a 50 percent cost reduction over the traditional PoS architecture, for example, by reducing the number of core router ports required to implement a network. RPR technology will play a critical role in allowing service providers to create high-speed networks that efficiently transport voice and data traffic while lowering both capital and on-going operational expenses. During the early phases of the RPR standardization process, when the specifications were in a state of flux, solutions for the most part were in-house FPGA and network processor-based developments, with all the size, cost and other constraints typically associated with those approaches. However, the majority of the features that will appear in the final RPR specification have been firmed-up in Draft 2.1, so the move to cost-effective, high-integration, low-power ASSPs, such as the Frea PoS Framer/RPR MAC, is becoming very attractive to equipment manufacturers.
The Infineon PoS Framer/RPR MAC supports both the IEEE 802.17 RPR standard (Draft 2.1) and the RFC 2892 Spatial Reuse Protocol (SRP) protocol, and is ideally suited to applications using either. It can also operate in a PoS framer-only mode, which gives carriers unparalleled flexibility in building legacy PoS networks that can later be configured to RPR when the need arises through a simple software upgrade. This flexibility lowers the total cost of ownership for carriers deploying RPR networks.
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